researchers in taiwan have been studying the effects of flipchip packaging on the performance of gallium nitride gan highelectronmobility transistors hemts szuping tsai et al, appl. phys. express, vol8, p034101, 2015. packaging three devices in parallel, the team from national chiaotung university and yuan ze university found increased output current and reduced onresistance, along with greater temperature insensibility. the researchers comment "superior performance such as this makes flipchip packaging a potential technology for highpower gan electronic applications."gan devices are being considered for replacements of silicon mos parts for power supplies, inverters for electric vehicles ev, photovoltaic pv inverters, and motor control for industry electronics. flipchippackaged transistors with lower parasitic effects could also benefit radiofrequency applications.the hemt devices that were used had a 2&mum gate length and 500&mum gate width, realized using a 10finger structure figure 1. the barrier material for the hemt was aluminium gallium nitride al0.25ga0.75n. the epitaxial structure &ndash 120nm aln buffer, 5.5&mum gan channel, 25nm algan barrier, and 4nm gan cap &ndash was grown on a 650&mum silicon substrate by metalorganic chemical vapor deposition mocvd.figure 1 a schematic layouts for single gan transistor. b schematic layouts for three gan transistors flipchip packaged in parallel. hollow purple outlines represent metal interconnects on substrate. c sem image of three gan hemts flipchip packaged in parallel.the researchers screened the three devices to be packaged for similar key electrical characteristics, "to ensure that all the devices connected in parallel had balanced current sharing". aln substrates were used as substrates for the flipchip packaging process using goldtogold thermocompression bonding at 250°c.the saturation drain current with 0v gate potential was about 1a for the three devices. this allowed the parallel devices to achieve almost 3a when packaged. the onresistance in the linear region was reduced to 1.3&omega, about onethird the value for the individual devices 4&omega.pulsed measurements with 0.02 duty cycle were performed to analyze thermal performance. pulsed operation avoids selfheating effects. &39calibration results&39 at various temperatures from measurements obtained with 0v gate and drain biases were compared with measurements with different quiescent drain bias voltages at 25°c to derive the respective channel temperatures.figure 2figure 2 estimated channel temperature as function of power dissipation.the pulsed measurements allowed the researchers to estimate the thermal resistance of the bare dies and the packaged device figure 2. packaging allowed the three transistors to operate at up to 30w power dissipation with a channel temperature restricted to less than 150°c. the bare dies reached 7w at 175°c.the researchers comment "this superior performance clearly indicates much better thermal management for applications of flipchip technology in highpower electronics." the packaged devices also demonstrated lower thermal sensitivity. the thermal resistance was less than a fifth that of the bare dies.tags gan hemts gan hemts mocvdvisit httpdx.doi.org10.7567apex.8.034101the author mike cooke is a freelance technology journalist who has worked in the semiconductor and advanced technology sectors since 1997. 
